Toshiba TLCS-900/H1 Series Manual page 384

3.16.1 Control Registers
Figure 3.16.1 shows the SDRAMC control registers. Setting these registers controls the
operation of SDRAMC.
SDACR1 Bit symbol
(0250H)
Read/Write
Reset State
Function Always
write "0"
Note 1: Issue mode register set command after changing <SBL1:0>. Exercise care in settings when changing from
"full-page read" to "1-word read". Please refer to "3.16.3 Limitations arising when using SDRAM".
SDACR2 Bit symbol
(0251H)
Read/Write
Reset State
Function
SDRCR Bit symbol
(0252H)
Read/Write
Reset State
Function
SDRAM Access Control Register 1
7 6 5
− −
SMRD
0 0 0
Always Mode
write "0" register set
delay time
0: 1 clock
1: 2 clocks
SDRAM Access Control Register 2
7 6 5
SDRAM Refresh Control Register
7 6 5
92CH21-382
4 3
SWRC SBST
R/W
0 0
Write Burst stop Selecting burst length
recover command (Note 1)
time
00: Reserved
0: Precharge
0: 1 clock
all
01: Full-page read, burst
1: 2 clocks
1: Burst stop
10: 1-word read, single
11: Full-page read, single
4 3
SBS SDRS1
0 0
Number of Selecting ROW address
banks size
0: 2 banks 00: 2048 rows (11 bits)
1: 4 banks 01: 4096 rows (12 bits)
10: 8192 rows (13 bits)
11: Reserved
4 3
SRS2
0
Refresh interval
000: 47 states
001: 78 states
010: 97 states
011: 124 states
TMP92CH21
2 1
SBL1 SBL0 SMAC
1 0
SDRAM
controller
0: Disable
1: Enable
write
write
write
2 1
SDRS0 SMUXW1 SMUXW0
R/W
0 0
Selecting address
multiplex type
00: TypeA (A9-)
01: TypeB (A10-)
10: TypeC (A11-)
11: Reserved
2 1
SRS1 SRS0 SRC
R/W
0 0
Auto
refresh
100: 156 states
0: Disable
101: 195 states
1: Enable
110: 249 states
111: 312 states
2009-06-19
0
0
0
0
0
0