Toshiba TLCS-900/H1 Series Manual page 194

3.10.1.1 System Configuration
The USB controller (UDC) consists of the following 3 blocks.
1. 900/H1 CPU I/F (details given in Section 3.10.2, below).
2. UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM
and 4 endpoint FIFO (details given in Section 3.10.3, below).
3. USB transceiver
Descriptor RAM
384 bytes
UDC core
I/F
PWM
DPLL
IFM
SIE
UDC
Request controller
Endpoint 0:
FIFO (64 bytes × 1)
Endpoint 1:
FIFO (64 bytes × 2)
FIFO
manager
Endpoint 2:
FIFO (64 bytes × 2)
Endpoint 3:
FIFO (8 bytes × 1)
Figure 3.10.1 UDC Block Diagram
92CH21-192
TMP92CH21
ADDRESS
900/H1 CPU
WR
interface
RD
D+
USB
transceiver
D−
2009-06-19