Toshiba TLCS-900/H1 Series Manual page 524

(10) 16-bit timer
Symbol Name Address
TMRB0
TB0RUN RUN 1180H
register
TMRB0 1182H
TB0MOD mode (Prohibit
register RMW)
TMRB0
1183H
flip-flop
TB0FFCR (Prohibit
control
RMW)
register
16-bit timer 1188H
TB0RG0L register 0 (Prohibit
low RMW)
16-bit timer 1189H
TB0RG0H register 0 (Prohibit
high RMW)
16-bit timer 118AH
TB0RG1L register 1 (Prohibit
low RMW)
16-bit timer 118BH
TB0RG1H register 1 (Prohibit
high RMW)
Capture
TB0CP0L register 0 118CH
low
Capture
TB0CP0H register 0 118DH
high
Capture
TB0CP1L register 1 118EH
low
Capture
TB0CP1H register 1 118FH
high
7 6 5
−
TB0RDE
R/W R/W
0 0
Double Always
buffer write "0"
0: Disable
1: Enable
− −
TB0CP0I TB0CPM1 TB0CPM0
R/W W*
0 0 1
Always write "0". Execute
software
capture
0: capture
1: Undefined
− −
TB0CT1
W*
1 1 0
Always write "11". TB0FF0 inversion trigger
0: Disable trigger
1: Enable trigger
Invert when
the UC value
is loaded in
to
TB0CP1H/L.
92CH21-522
4 3 2
I2TB0 TB0PRUN
R/W R/W
0 0
IDLE2
TMRB0
0: Stop
prescaler
1: Operate
0: Stop and clear
1: Run (Count up)
TB0CLE
R/W
0 0 0
Capture timing Control
00: Disable up counter
01: Reserved
0: Disable
10: Reserved
clearing
11: TA1OUT↑
1: Enable
TA1OUT↓
clearing
TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0
R/W
0 0 0
Invert when Invert when Invert when
the UC value the UC value the UC value
is loaded in matches the matches the
to value in value in
TB0CP0H/L. TB0RG1H/L TB0RG0H/L
−
W
Undefined
−
W
Undefined
−
W
Undefined
−
W
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
TMP92CH21
1 0
TB0RUN
R/W
0
UP counter
(UC10)
TB0CLK1 TB0CLK0
0 0
TMRB0 source clock
00: Reserved
01: φT1
10: φT4
11: φT16
W*
1 1
Control TB0FF0
00: Invert
01: Set
10: Clear
11: Don't care
* Always read as "11"
2009-06-19