Toshiba TLCS-900/H1 Series Manual page 199

bit Symbol
USBINTFR1
(07F0H)
Read/Write
Reset State
Function
Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released)
7 6
INT_URST_STR
INT_URST_END
R/W R/W
0 0
When read 0: Not generate interrupt
1: Generate interrupt
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, a low power
dissipation system can be built. However, the method of use is limited as below.
Shift to IDLE1 mode :
Execute Halt instruction when the INT_SUS or INT_CLKSTOP flag is "1" (SUSPEND state)
Release from IDLE1 mode :
Release Halt state by INT_RESUME or INT_CLKON request (request of release SUSPEND)
Release Halt state by INT_URST_STR or INT_URST_END request (request of RESET)
• INT_URST_STR (Bit7)
This is the flag register for INT_URST_STR ("USB reset" start - interrupt).
This is set to "1" when the UDC starts to receive a "USB reset" signal from a
USB-host.
An application program has to initialize the whole UDC with this interrupt.
• INT_URST_END (Bit6)
This is the flag register for INT_URST_END ("USB reset" end - interrupt).
This is set to "1" when the UDC receives a "USB reset end" signal from a
USB-host.
•
INT_SUS (Bit5)
This is the flag register for INT_SUS (suspend - interrupt).
This is set to "1" when the USB changes to "suspend status".
• INT_RESUME (Bit4)
This is the flag register for INT_RESUME (resume - interrupt).
This is set to "1" when the USB changes to "resume status".
• INT_CLKSTOP (Bit3)
This is the flag register for INT_CLKSTOP (enables stopping of the clock
supply - interrupt).
This is set to "1" after the USB changes to "suspend status". Set
USBCR1<USBCLKE> to "0" to stop the clock after detecting this interrupt if
needed.
• INT_CLKON (Bit2)
This is the flag register for INT_CLKON (enable starting of the clock supply
- interrupt).
This is set to "1" after changing to "resume status" or when the UDC started
to receive a "USB reset" signal from a USB-host. In case the clock has be
stopped, set USBCR1<USBCLKE> to "1" to start the clock after detecting this
interrupt if needed.
5 4
INT_SUS INT_RESUME INT_CLKSTOP
R/W R/W
0 0
When write 0: Clear flag
1: −
92CH21-197
3 2
INT_CLKON
R/W R/W
0 0
TMP92CH21
1 0
2009-06-19