Toshiba TLCS-900/H1 Series Manual page 181

1. Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the
TXD0 and SCLK0 pins respectively each time the CPU writes data to the
transmission buffer. When all data is output, INTES0<ITX0C> will be set to
generate the INTTX0 interrupt.
Timing of transmitted
data writing
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 interrupt
request)
Figure 3.9.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode) (Channel 0)
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
input becomes active after the data has been written to the transmission buffer by
the CPU.
When all data is output, INTES0<ITX0C> will be set to generate an INTTX0 interrupt.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
TXD0
ITX0C
(INTTX0 intterrupt
reqest)
Figure 3.9.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode) (Channel 0)
Bit0 Bit1
Bit0 Bit1 Bit5
92CH21-179
TMP92CH21
(Internal
Bit6 Bit7
Bit6 Bit7
2009-06-19
Clock timing)