Toshiba TLCS-900/H1 Series Manual page 354

Original cmos 32-bit microcontroller

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3.14.3.7 Timing Diagram of LD Bus

The TMP92CH21 can select to display RAM for external SRAM: Available to set

WAIT, internal SRAM and external SDRAM: 16, 32, 64, 128, 256 and 512 Mbits.

As a 480-byte FIFO buffer is built into this LCDC, the LD bus speed can be

The speed can be selected from 3 kinds of cycle: (f

LD bus data: LD11 to LD0 is out at rising edge of LCP0, LCD driver receives at

falling edge of LCP0.

Note: If the LCP cycle is too slow it may not transfer correctly.

If LCP cycle is not set at a suitable speed with respect to the refresh rate, LD bus

data will not transfer correctly. t

Data transmission must finish in t

time. For setting of SCC, refer to "basic clock setting" of "refresh rate setting".

The kind of display memory and display mode determine LCP speed. In other words,

when the setting is too fast , there will be not enough transmission data in FIFO, and

LCD data will not transfer correctly.

Figure 3.14.9 Selection of LCP Cycle

[Hz]) × 16 × (SCC+1)

time is shown in the equation below.

time. Set SCC clock and LCP0 speed to be less

/4, and fSYS/8)

Tmp92ch21fg Jtmp92ch21