Toshiba TLCS-900/H1 Series Manual page 121

3.6.4 ROM Control (Page mode)
This section describes ROM page mode accessing and how to set registers. ROM page
mode is set by the page ROM control register.
(1) Operation and how to set the registers
The TMP92CH21 supports ROM access of the page mode. ROM access of the page
mode is specified only in block address area 2.
ROM page mode is set by the page ROM control register (PMEMCR). Setting
<OPGE> of the PMEMCR register to "1" sets the memory access of the block address
area to ROM page mode access.
The number of read cycles is set by the <OPWR1:0> of the PMEMCR register.
<OPWR1> <OPWR0>
Note: Set the number of waits ("n") using the control register (BnCSL) in each block
The page size (the number of bytes) of ROM in the CPU size is set by the <PR1:0> of
the PMEMCR register. When data is read out up to the border of the set page, the
controller completes the page reading operation. The start data of the next page is read
in the normal cycle. The following data is set to page read again.
SDCLK
t
CYC
A0 to A23
CS 2
RD
D0 to D31
Figure 3.6.2 Page mode access Timing (8-byte example)
<OPWR1:0> (PMEMCR register)
0 0
0 1
1 0
1 1
address area.
<PR1:0> Bit (PMEMCR register)
<PR1> <PR0>
0 0
0 1
1 0
1 1
+0
t t
AD3
t t
RD3
Data
input
92CH21-119
Number of Cycle in a Page
1 state (n-1-1-1 mode) (n ≥ 2)
2 state (n-2-2-2 mode) (n ≥ 3)
3 state (n-3-3-3 mode) (n ≥ 4)
(Reserved)
ROM Page Size
64 bytes
32 bytes
16 bytes (Default)
8 bytes
+1 +2
t
AD2 AD2
t
HA HA
Data
input
TMP92CH21
+3
t
HA
t
AD2
t
HR
t
HA
Data Data
input input
2009-06-19