Toshiba TLCS-900/H1 Series Manual page 402

4) ID read
The ID read sequence is as follows.
(1) ND0FMCR:
(2) ND0FDTR:
(3) ND0FMCR:
(4) ND0FDTR:
(5) ND0FMCR:
(6) ND0FDTR:
(7) ND0FDTR:
3.17.3.2 ECC Control
The NDFC contains the ECC calculating circuits. The circuits are controlled by
ND0FMCR. This circuit executes ECC data calculation. However, ECC comparison
and error correction is not executed. This must be executed using software.
The calculated ECC data can be read from the NDECCRD register when ND0FMCR
is 0xD0 (write mode) or 0x50 (read mode). This is 6-byte data, and six NDECCRD read
operations are required. The order of the data is as follows.
Set 0x1D for NDCLE signal enable and command mode.
Set 0x90 for the ID Read command.
Set 0x1E for NDALE signal enable and the address mode.
Set 0x00.
Set 0x1C for the data mode without ECC calculation.
Read Maker code.
Read Device code.
First data: LPR [7:0]
Second data: LPR [15:8]
Third data: CPR [5:0], 2'b11
Fourth data: LPR [23:16]
Fifth data: LPR [31:24]
Sixth data: CPR [11:6], 2'b11
92CH21-400
TMP92CH21
2009-06-19