Toshiba TLCS-900/H1 Series Manual page 273

(b) Dual packet mode
In dual packet mode, FIFO is divided into A and B packet, and is controlled
according to priority in hardware. It can be performed at once, transmitting and
receiving data to USB host and exchanges to external of UDC. When it reads out
data from FIFO for receiving, confirm condition of two packets, and consider the
order of priority. If it has received data to two packets, the UDC outputs from first
receiving data by FIFO that can be accessed are common in two packets. EPx_SIZE
register is prepared for both packet A and packet B. First, the CPU must recognize
the data number of first receiving packet by PKT_ACTIVE bit. If PKT_ACTIVE bit
was set to 1, that packet is received first. Packet A and packet B set data turn
about always.
This sequence is shown below.
Wait receiving data
DATASET register
DATASET = 0
DATASET register
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
DATASET = 1
SIZE register
• Read size of receiving data from relevant endpoint
• There are 3 cases by setting bit of DATASET:
Only A: Read number of sizeA register
Only B: Read number of sizeB register
Both of A and B: Read number of sizeA + B register
• Clear receiving data in FIFO
• Clear relevant bit in DATASET register
Figure 3.10.15 Receiving Sequence in Dual Packet Mode
IDLE
Receiving valid data
• Set bit of EPx_DSET_A (B)
• Assert EPx_DATASET signal
Interrupt by EPx_FULL_A (B)
Check DATASET register
• Confirm Size of SIZE_A_L
• Confirm Size of SIZE_A_H
• Confirm Size of SIZE_B_L
• Confirm Size of SIZE_B_H
92CH21-271
TMP92CH21
2009-06-19