Toshiba TLCS-900/H1 Series Manual page 436

Write to FIFO
<TXE>
I2SWS pin
I2SCKO pin
I2SDO pin
<BUSY>
INTI2S
I2SWS pin
10 MHz
I2SCKO pin
I2SDO pin LSB MSB
Bit7
(3) Notes
1) INTI2S timing
2) I2SCTL0<TXE>
stopped by writing "0".
automatically from right to left in order, alternately.
changes to "0" in the INTI2S interrupt routine.
immediately.
3) FIFO size
to use all data, but please use the even numbers (2, 4 ... 16).
4) I2SCTL0<I2SFSEL>
data is fixed at "0".
5) Address for I2SBUFR and I2SBUFL
instruction". A "byte data load instruction" cannot be used.
selectable from 0808H to 080BH.
1
Figure 3.20.4 Whole
LSB
Bit6 Bit0
Figure 3.20.5 Detail
INTI2S is generated after the last data of FIFO is loaded to the internal shifter.
FIFO is now empty and it is possible to write the next data.
A transmission is started by programming "1" to the <TXE> register and
After<TXE> is programmed "1" once, the transmission is repeated
If a transmission should be stopped, program "0" to <TXE> after <BUSY>
When <TXE> is programmed "0" during transmitting, transmitting stops
A 16-byte FIFO is provided for both right and left channels. It is not necessary
Write "1" to <I2SFSEL> and use the right channel FIFO for monaural.
It is not necessary to write data to the left channel FIFO. Channel transmission
If writing data to I2SBUFR or I2SBUFL, use "word or long word data load
The address of I2SBUFR selectable from 0800H to 0803H, and I2SBUFL is
92CH21-434
2
Timing Diagram
MSB
Bit7 Bit6
Timing Diagram
TMP92CH21
16 1
LSB MSB
Bit0 Bit7
2009-06-19