Toshiba TLCS-900/H1 Series Manual page 368

(Notes on settings)
1. LCP0 cycle: LCP0=f
LCP0 cycle is generated by system clock and value of LCDMODE0<SCPW1:0>
2. LCP1 cycle: LCP1= f
LCP1 cycle is generated by value of LCDSCC register.
High level width of LCP1 is fixed to f
As indicated above, the cycles of LCP0 and LCP1 are able to set each other.
There are some limitations to settings of LD bus speed and LCDSCC.
High level width of LLP is adjusted every f
of LLP when transmission speed of the LD bus is set to 2-Clock. LLP is also adjusted every
4-clock of LLP when transmission speed of the LD bus is set to 4-clock of LCP0.
Setting method is the same as in the STN case, following the calculation below.
[Hz]
f
BCD
FP
SCC
f
BCD
Frame correction function is the same as in the STN case.
3. LCP1 Setting: Vertical front porch is determined by LCDCCR0.
Vertical front porch is determined by the above 3bits; LCDCCR0<PCPV2:0>.
Vertical back porch is controlled by the pulse number which is <PCPV2:0> subtracted
from LCDFFP<FP9:0> as explained in the SR mode section.
× n (n=2, 4, 8: transmission speed of LD bus)
SYS
× 16 × (SCC + 1)
SYS
Segment Transmission
Size Speed of
LD bus
64
128
160
256
320
: Frame frequency (Refresh rate: LBCD cycle)
: FP [9:0] FFP register setting value
: SCC [7:0] LSCC register setting value
[Hz] / ((SCC+1) × 16 × FP)
[Hz] = f
SYS
× 4 times. (Positive edge)
SYS
Minimum
LCDSCC
value
2 9
4 17
8 33
2 17
4 33
8 65
2 21
4 41
8 81
2 33
4 65
8 129
2 41
4 81
8 161
× 8 cycle. However, LLP is adjusted every 2-clock
SYS
92CH21-366
TMP92CH21
2009-06-19