Toshiba TLCS-900/H1 Series Manual page 472

(1) Read cycle (0 waits)
X1
SDCLK
WAIT
A0~A23
CSn
R/
W
RD
D0~D31
SRxxB
SRWR
Note: The phase relation between X1 input signal and the other signals is undefined.
The above timing chart is an example.
t
OSC
t
CYC
t t
CH CL
t
TK
t
AD
t t
AR RK
t
RRH
t
SBA
92CH21-470
t
KT
t
RR
t
RD
Data input
TMP92CH21
t
HA
t
HR
2009-06-19