Toshiba TLCS-900/H1 Series Manual page 218

FIFO_DISABLE (Bit1)
0: FIFO enabled
1: FIFO disabled
STAGE_ERROR (Bit0)
0: SUCCESS
1: ERROR
This bit symbol shows FIFO status, except for EP0.
If the FIFO is set to disabled, the UDC transmits NAK
handshake for all transfers. Disabled or enabled status is set by
the COMMAND register. This bit is cleared to "0" when transfer
type is changed.
This bit symbol shows that the status stage has not been
terminated correctly. ERROR is set when a status stage is not
terminated correctly and a new SETUP token is received.
When this bit is "1", this bit is cleared to "0" by read
EP0_STATUS register. This bit is not cleared even if normal
control transfer or other transfer is executed after it. To clear,
read this bit. When software transaction is finished and UDC
writes EOP register, UDC shifts to status register and waits for
termination of status stage. In this case, if software is needed to
confirm that the status stage has been terminated correctly, when
a new request flag is received, it is possible to confirm whether or
not the last request was terminated correctly. It can also be
confirmed, when a new request flag is asserted, whether or nor
the last request was cancelled before completion.
92CH21-216
TMP92CH21
2009-06-19