Toshiba TLCS-900/H1 Series Manual page 29

3.3.4 Clock Doubler (PLL)
PLL outputs the f
low-speed-frequency oscillator can be used, even though the internal clock is
high-frequency.
A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed
before use.
As with an oscillator, this circuit requires time to stabilize. This is called the lock up time
and it is measured by a 16-stage binary counter. Lock up time is about 1.6 ms at f
MHz.
Note 1: Input frequency range for PLL
The input frequency range (High-frequency oscillation) for PLL is as follows:
f
OSCH
Note 2: PLLCR0<LUPFG>
The logic of PLLCR0<LUPFG> is different from 900/L1's DFM.
Exercise care in determining the end of lock up time.
The following is an example of settings for PLL starting and PLL stopping.
Example 1: PLL starting
PLLCR0 EQU
PLLCR1 EQU
LD
LUP: BIT
JR
LD
X: Don't care
<PLLON>
<FCSEL>
PLL output: f
PLL
Lock up timer
<LUPFG>
System clock f
SYS
clock signal, which is four times as fast as f
PLL
= 6 to 10 MHz (V = 3.0 to 3.6 V)
CC
10E8H
10E9H
(PLLCR1), 1 X X X X X X X B ;
5, (PLLCR0)
Z, LUP
(PLLCR0), X 1 X X X X X X B ;
Counts up by
During lock up
Starts PLL operation and
starts lock up
92CH21-27
Enables PLL operation and starts lock up
;
Detects end of lock up.
;
Changes fc from 10 MHz to 40 MHz.
f
OSCH
After lock up
Changes from 10 MHz to 40 MHz
Lock up ends
TMP92CH21
. A
OSCH
= 10
OSCH
.
2009-06-19