Toshiba TLCS-900/H1 Series Manual page 158

(b) Sub routine (Bank 0 in LOCAL-Y)
Logical Physical
Address Address
400000H 000000H
4000xxH 0000xxH
5000yyH 1000yyH
•
No.17 and No.18 are settings for BANK 1 of LOCAL-Y. In this case, LCD display data is
written to SRAM by CPU.
So, (LOCALWY) and (LOCALLY) should be set to the same BANK 1.
•
No.19 is a setting for BANK 0 of LOCAL-Z to read data from character ROM.
•
No.20 and No.21 are instructions to read data from character ROM. When CPU outputs
800000H address, this MMU will convert and output 000000H address to external address
bus: A23 to A0. And
the CS2 area at the same time.
These instructions allow the CPU to read data from character ROM.
•
No.23 is an instruction which changes the program BANK number in the local area. This
setting is disabled.
•
No.24 and No.25 are instructions to write data to SRAM. When CPU outputs 400000H
address, this MMU will convert and output 200000H address to external address bus: A23
to A0. And for SRAM will be asserted because its logical address is in the CS1area at
CS1
the same time.
These instructions allow the CPU to write data to SRAM.
•
No.28 and No.29 are settings to set LCD starting address to LCD controller. When LCDC
outputs 400000H address in DMA cycle, this MMU will convert and output 200000H
address to external address bus: A23 to A0. And
its logical address is in the CS1 area at the same time.
These instructions allow the LCDC to read data from SRAM.
•
No.30 is an instruction to start LCD display operation.
No Instruction
16 org 400000H
17 ld (localwy), 81H
18 ld (locally), 81H
19 ld (localrz), 80H
20 ld xiy, 800000H
21 ld wa, (xiy)
22 :
23 ld (localpy), 82H
24 ld xix, 400000H
25 ld (xix), bc
26 :
27 :
28 ld xiz, 400000H
29 ld (lsarcl), xiz
30 ld (lcdctl0), 01H
31 :
32 ret
for NOR flash will be asserted because its logical address is in
CSZA
92CH21-156
Comment
;
; BANK 1 in LOCAL-Y is set as write data for
LCD display RAM
; BANK 1 in LOCAL-Y is set as LCD display data
for LCD display RAM
; BANK 0 in LOCAL-Z is set as read data for
character ROM
; Index address register to read character ROM
; Reading character ROM
; Convert it to display data
;
; Index address register to write LCD
display data
; Writing LCD display data
; Setting LCD controller
;
; Setting LCD start address to LCDC
;
; Start LCD display operation
;
;
for SRAM will be asserted because
CS1
TMP92CH21
2009-06-19