Toshiba TLCS-900/H1 Series Manual page 345
Original cmos 32-bit microcontroller
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•
Monochrome: 1 bpp (bit per pixel)
Display memory image
Address 0
LSB
D0
0
1
2
3
4
5
6
LD bus output sequence
4-bit width A type
→
→
LD0
0
4
8
→
→
LD1
1
5
9
→
→ 10 → 14 ...
LD2
2
6
→
→ 11 → 15 ...
LD3
3
7
LD4
Not use
LD5
Not use
LD6
Not use
LD7
Not use
Note: This mode is not supported by 8 bit width B type.
•
4 grayscales (2 bpp)
Display memory image
Address 0
LSB
D0
0
1
2
3
4
5
6
1 pixel
LD bus output sequence
4-bit width A type
→ 9-8
→ 17-16 ...
LD0
1-0
→ 11-10 → 19-18 ...
LD1
3-2
→ 13-12 → 21-20 ...
LD2
5-4
→ 15-14 → 23-22 ...
LD3
7-6
LD4
Not use
LD5
Not use
LD6
Not use
LD7
Not use
Note: This mode is not supported by 8 bit width B type.
Figure 3.14.2 Relation of Memory Map Image and Output Data (1)
Address 1
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4-bit width B type
→ 12 ...
4 →
LD0
→ 13 ...
5 →
LD1
6 →
LD2
7 →
LD3
LD4
Not used
LD5
Not used
LD6
Not used
LD7
Not used
Address 1
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4-bit width B type
LD0
9-8
11-10 → 3-2 → 27-26 ...
LD1
13-12 → 5-4 → 29-28 ...
LD2
15-14 → 7-6 → 31-30 ...
LD3
LD4
Not used
LD5
Not used
LD6
Not used
LD7
Not used
92CH21-343
Address 2
→ 12 →
...
0
8
→ 13 →
...
1
9
→ 14 → 10 ...
2
→ 15 → 11 ...
3
Address 2
→ 1-0 → 25-24 ...
TMP92CH21
Address 3
MSB
D31
8-bit width A type
→
...
LD0
0
8
→
...
LD1
1
9
→ 10 ...
LD2
2
→ 11 ...
LD3
3
→ 12 ...
LD4
4
→ 13 ...
LD5
5
→ 14 ...
LD6
6
→ 15 ...
LD7
7
Address 3
MSB
D31
8-bit width A type
→ 17-16 ...
LD0
1-0
→ 19-18 ...
LD1
3-2
→ 21-20 ...
LD2
5-4
→ 23-22 ...
LD3
7-6
→ 25-24 ...
LD4
9-8
→ 27-26 ...
LD5
11-10
→ 29-28 ...
LD6
13-12
→ 31-30 ...
LD7
15-14
2009-06-19
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