Toshiba TLCS-900/H1 Series Manual page 111

3.6.3 Basic Functions and Register Setting
This section describes the setting of the block address area, the connecting memory and
the number of waits out of the memory controller's functions.
(1) Block address area specification
The block address area is specified by two registers.
The memory start address register (MSARn) sets the start address of the block
address areas. The memory controller compares the register value and the address
every bus cycle. The address bit which is masked by the memory address mask register
(MAMRn) is not compared by the memory controller. The block address area size is
determined by setting the memory address mask register. The value that is set to the
register is compared with the block address area on the bus. If the result is a match,
the memory controller sets the chip select signal (CSn) to "low".
(i) Memory start address register setting
The MS23 to MS 16 bits of the memory start address register correspond with
addresses A23 to A16 respectively. The lower start addresses A15 to A0 are always
set to address 0000H.
Therefore the start addresses of the block address area are set to all 64 Kbytes
of addresses 000000H to FF0000H.
(ii) Memory address mask register setting
The memory address mask register determines whether an address bit is
compared or not. In register setting, "0" is "compare", and "1" is "do not compare".
The address bits that can be set depends on the block address area.
The upper bits are always compared. The block address area size is determined
by the result of the comparison.
The size to be set depending on the block address area is as follows.
Size (bytes)
256
CS area
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CS0
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CS1
CS2 to CS3
Note: After reset release, only the control register of the block address area 2 is valid. The control register
of block address area 2 has the <B2M> bit. If the <B2M> bit is set to "0", block address area 2 is set
to addresses 000000H to FFFFFFH. (This is the state following reset release .) If the <B2M> bit is
set to "1", the start address and the address area size are set, as in the other block address areas.
Block address area 0: A20 to A8
Block address area 1: A21 to A8
Block address area 2 to 3: A22 to A15
512 32 K 64 K
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92CH21-109
128 K 256 K 512 K
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TMP92CH21
1 M 2 M 4 M 8 M
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2009-06-19
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