Toshiba TLCS-900/H1 Series Manual page 386

3.16.2 Operation Description
(1) Memory access control
SDRAM controller is enabled when SDACR1<SMAC> = 1. And then SDRAM control
signals ( SDCS , SDRAS , SDCAS , SDWE , SDLLDQM, SDLUDQM, SDULDQM,
SDUUDQM, SDCLK and SDCKE) are operating during the time CPU or LCDC
accesses CS1 or CS2 area.
1. Address multiplex function
In the access cycle, outputs row/column address through A0 to A15 pin. And
multiplex width is decided by setting SDACR2<SMUXW0:1> of use memory size. The
relation between multiplex width and Row/Column address is shown in Table 3.16.3.
TMP92CH21
Pin Name
TypeA
<SMUXW> "00"
A0 A9
A1 A10
A2 A11
A3 A12
A4 A13
A5 A14
A6 A15
A7 A16
A8 A17
A9 A18
A10 A19
A11 A20
A12 A21
A13 A22
A14 A23
A15 EA24
* AP: Auto Precharge
2. Burst length
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single
write. When the LCDC accesses the SDRAM, the burst length is fixed to full page.
SDRAM access cycle is shown in Figure 3.16.2 and Figure 3.16.3.
SDRAM access cycle number does not depend on the settings of B1CSL and B2CSL
registers. In the full page burst read cycle, a mode register set cycle and a precharge
cycle are automatically inserted at the beginning and end of a cycle.
(2) Instruction executing on SDRAM
The CPU can execute instructions on SDRAM. However, the following functions do
not operate.
a)
b)
These operations must be executed by another memory such as the built-in RAM.
Table 3.16.1 Address Multiplex
Address of SDRAM Accessing Cycle
Row Address
TypeB
<SMUXW> "01" <SMUXW> "10"
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
EA24
EA25
Executing HALT instruction
Execute instructions that write to SDCMM register
92CH21-384
TypeC 16-Bit Data Bus Width
B1CSH<BnBUS> = "01"
A11 A1
A12 A2
A13 A3
A14 A4
A15 A5
A16 A6
A17 A7
A18 A8
A19 A9
A20 A10
A21 AP *
A22
A23
EA24
EA25
EA26
TMP92CH21
Column Address
32-Bit Data Bus Width
B1CSH<BnBUS> = "10"
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
AP *
Row address
2009-06-19