Toshiba TLCS-900/H1 Series Manual page 333

3.14 LCD Controller
This LSI incorporates two types of liquid crystal display driving circuit for controlling LCDs.
One circuit supports an internal RAM LCD driver that can store display data in the LCD driver
itself, and the other circuit supports a shift-register type LCD driver that must serially transfer
the display data to the LCD driver for each display picture.
Software-programmable screen size supported.
This LCDC supports 2 bpp (bit per pixel: 4 grayscales), 3 bpp (8 grayscales), 4 bpp (16
grayscales) 8 bpp, (256 colors) and 12 bpp (4096 colors) for dot matrix panels. In passive matrix
STN mode, it supports 8 bpp (256 colors) out of a palette of 4096 colors. And in active matrix
TFT mode, it supports 8 bpp (256 colors) and 12 bpp (4096 colors).
Data bus width for 8- or 12-bit TFT panels is supported, and 8- and 4-bit wide LCD panel data
bus for STN panels, plus hardware panning (soft horizontal and vertical scrolling).
1) Shift register type LCD driver control mode (SR mode)
This mode is for monochrome STN or color STN panels. Before setting start register, set
the mode of operation, the start address of source data save memory and LCD size to
control register.
After setting start register, the LCDC outputs a bus release request to the CPU and reads
data from source memory.
The LCDC then transmits LCD size data to the external LCD driver through the special
LCDC data bus (LD11 to LD0). At this time, the control signals connected to the LCD driver
output the specified waveform which is synchronized with the data transmission. After
display data reading from RAM is completed, the LCDC cancels the bus release request and
the CPU will re-start.
In the TMP92CH21, SRAM and SDRAM burst mode can be used for the external display
RAM.. 16-Kbytes of internal RAM are available for use as display RAM. As internal RAM
access is very fast (32-bit bus width, 1 SYSCLK read/write), it is possible to reduce CPU
load to a minimum, enabling LCDC DMA.
2) Color display mode for TFT panel
The data transmission process is as above in SR mode. LD11 to LD0; 8 bpp RGB (R: 3, G:
3, B: 2) and 12 bpp RGB (R: 4, G: 4, B: 4), LCP0, LFR, LLP and LDIV: invert data line
control the TFT source driver.. And besides signals LCP1 and LBCD, OE can also control
details of output timing for control of TFT gate driver.
3) Internal RAM LCD driver control mode (RAM mode)
Data transmission to the LCD driver is executed CPU command. After setting operation
mode to control register, when CPU command is executed the LCDC outputs chip select
signal to the LCD driver connected externally by control pin (LCP0 etc.). Therefore control
of data transmission numbers corresponding to LCD size is controlled by CPU command.
92CH21-331
TMP92CH21
2009-06-19