Toshiba TLCS-900/H1 Series Manual page 476

SDRAM Controller AC Characteristics
4.3.3
No. Parameter
1 Ref/active to ref/active command period
2 Active to precharge command period
3 Active to read/write command delay
time
4 Precharge to active command period
5 Active to active command period
6 Write recovery time (CL* = 2)
7 Clock cycle time (CL* = 2)
8 Clock high level width
9 Clock low level width
10 Access time from clock (CL* =2)
11 Output data hold time
12 Data in setup time
13 Data in hold time
14 Address setup time
15 Address hold time
16 CKE setup time
17 Command setup time
18 Command hold time
19 Mode register set cycle time
:
CL* CAS latency.
AC measuring conditions
• Output level: High = 0.7 VCC, Low = 0.3 VCC, C
• Input level: High = 0.9 VCC, Low = 0.1 VCC
Variable
Symbol
Min Max
t 2T
RC
t 2T 12210
RAS
t T
RCD
t T
RP
t 3T
RRD
t T
WR
t T
CK
0.5T − 15
t
CH
0.5T − 15
t
CL
T − 30
t
AC
t 0
OH
T − 35
t
DS
T − 5
t
DH
0.75T − 30
t
AS
0.25T − 9
t
AH
0.5T − 15
t
CKS
0.5T − 15
t
CMS
0.5T − 15
t
CMH
t T
RSC
= 50 pF
L
92CH21-474
TMP92CH21
40 MHz 36 MHz 27 MHz
100 111 148
100 111 148
50 55.5 74
50 55.5 74
150 166.5 222
50 55.5 74
50 55.5 74
10 12.7 22
10 12.7 22
20 25.5 44
0 0 0
15 20.5 39
45 50.5 69
7.5 11.6 25.5
3.5 4.8 9.5
10 12.7 22
10 12.7 22
10 12.7 22
50 55.5 74
2009-06-19
Unit
ns