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Toshiba TLCS-900/H1 Series Manual page 373

Original cmos 32-bit microcontroller
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3.14.6
Built-in RAM Type LCD driver Mode
3.14.6.1 Description of Operation
Data transmission to the LCD driver is executed by a transmit instruction from the
CPU.
After setting operation mode of to the control register, when a CPU transmit
instruction is executed the LCDC outputs a chip select signal to the LCD driver
connected externally by the control pin (LCP0...). Therefore control of data
transmission numbers corresponding to LCD size is controlled by CPU instruction.
There are 2 kinds of LCD driver address in this case, which are selected by the
LCDCTL<MMULCD> register.
3.14.6.2 Random Access Type
This corresponds to address direct writing type LCD driver when <MMULCD> = "1".
The transmission address can also assign the memory area 3C0000H − 3FFFFF, the
four areas each being 64 Kbytes.
Interface and access timing are the same as for normal memory. Refer to the
memory access timing section.
Table 3.14.2 Racdom Access Type Built-in RAM Type LCD driver
Address
3C0000H to
3CFFFFH
3D0000H to
3DFFFFH
3E0000H to
3EFFFFH
3F0000H to
3FFFFFH
Function
Built-in RAM LCDD1
Built-in RAM LCDD2
Built-in RAM LCDD3
Built-in RAM LCDD4
92CH21-371
Chip Enable Terminal
LCP0
LLP
LFR
LBCD
TMP92CH21
2009-06-19

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