Toshiba TLCS-900/H1 Series Manual page 369

4. LLP Setting: Set up time is determined by LCDCCR1.
Set up time of LLP (horizontal front porch) is set in LCDCCR1 register. This is
called "Delay control 2". 1 pulse of this set up time in LCDCCR1 register is equal to 8
times of fsys regardless of LCP0 and LCP1. The set up time has offset time; fsys×14 or
more. If "0" is written in LCDCCR1 register, fsys×14.5 or more of time is delayed. This
offset time changes according to the setting conditions. The cycle of LCP1 is
determined by (the value of LCDSCC register +1) × fsys × 16, thus horizontal back
porch is the time where offset time and set up time are subtracted from the cycle of
LCP1.
5. LLP High width: High width of LLP is determined by LCDCCR2.
The pulse number of LCP0 in LCDCCR2 means enable time of LLP. This register
determines "High width" time as mentioned above. 1 pulse of this time in LCDCCR2
register is equal to 8 times of fsys regardless of LCP0 and LCP1. If "0" is written in
LCDCCR2 register, High level is output during the period that the valid data is output
from the LD bus.
(In Mode1, high level is kept during one more LCP0 than valid data.)
6. LDIV: Enable/disable of Auto Invert function is determined by LCDMODE1<AUTOINV>.
If "1" is written in LCDMODE1<AUTOINV> bit, the LCD controller monitors the
status of the LD bus. The LCDC compares the value of previous data with the data
supposed to be sent. If more than a majority of all the LD bus change, LDIV outputs
"1" and the LCDC inverts the LD bus value that was supposed to be sent.
For example, if 4096 color(12bit ： LD11 to LD0) and the data changes from
000000000000→111111111111, the data remains 000000000000→000000000000 and
only LDIV changes 0→1.
This is effective in reducing noise or power consumption where the LCD driver has
an LDIV pin.
92CH21-367
TMP92CH21
2009-06-19