Toshiba TLCS-900/H1 Series Manual page 271

(a) Single packet mode
This is data sequence of single packet mode when CPU bus interface is used.
Figure 3.10.13 is receiving sequence. Figure 3.10.14 is transmitting sequence. This
chapter focuses on access to FIFO. For Data sequence with USB host refer to
chapter 5.
Endpoint 0 cannot be changed to exclusive single packet mode. Endpoints 1 to 3
can be changed between single packet and dual packet by setting Epx_SINGLE
register. Do not change packet when transferring.
Wait receiving data
DATASET = 0
DATASET register
• Check bit of EPx_DSET_A
DATASET = 1
SIZE register
RD receiving data of size in relevant
endpoint
Figure 3.10.13 Receiving Sequence in Single Packet Mode
IDLE
Receive valid data
DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
Interrupt by EPx_FULLA
Check DATASET register
• Size of SIZE_A_L confirmation
•
Size of SIZE_A_H confirmation
• Clear receiving data in FIFO
• Clear relevant bit of DATASET
register
92CH21-269
TMP92CH21
2009-06-19