Hitachi H8/3672 Series Hardware Manual page 5

This LSI is a single-chip microprocessor made up of the high-speed H8/300H CPU as its core, and
the peripheral functions required to configure a system. The H8/300H CPU has an instruction set
that is compatible with the H8/300 CPU
This LSI is equipped with ROM, RAM, an 8-bit timer (TMR), a 16-bit timer, a watchdog timer
(WDT), two types of serial communication interfaces (SCIs), a 10-bit A/D converter, and I/O
ports as on-chip peripheral modules. This LSI is suitable for use as an embedded processor for
high-level control systems. Its on-chip ROM is flash memory (F-ZTAT
flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of
mass production to full-scale mass production. This is particularly applicable to application
devices with specifications that will most probably change.
TM
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8/3672 Series in the
design of application systems. Members of this audience are expected to
understand the fundamentals of electrical circuits, logical circuits, and
microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of the H8/3672 Series to the above audience.
Refer to the H8/300H Series Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
In order to understand the details of the CPU's functions
Read the H8/300 Series Programming Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in Appendix A,
On-Chip I/O Registers.
Examples: Register name:
Bit order:
Preface
The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB is on the left and the LSB is on the right.
TM
*) that provides
Rev. 2.0, 03/01, Page
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