Hitachi H8/3672 Series Hardware Manual page 109

Set block start address as verify address
H'FF dummy write to verify address
Increment address
No
No
Figure 7-4 Erase/Erase-Verify Flowchart
Erase start
SWE bit ← 1
Wait 1 µs
n ← 1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 µs
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Wait 2 µs
Read verify data
No
Verify data + all 1s ?
Yes
Last address of block ?
Yes
EV bit ← 0
Wait 4 µs
All erase block erased ?
Yes
Yes
SWE bit ← 0
Wait 100 µs
End of erasing
n ← n + 1
EV bit ← 0
Wait 4µs
Yes
n ≤100 ?
No
SWE bit ← 0
Wait 100 µs
Erase failure
Rev. 1.0, 03/01, page 85 of 280