Serial Data Reception (Clocked Synchronous Mode) - Hitachi H8/3672 Series Hardware Manual

13.5.4

Serial Data Reception (Clocked Synchronous Mode)

Figure 13-12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 13-13 shows a sample flow
chart for serial data reception.
Serial
clock
Serial
Bit 7
data
RDRF
OER
LSI RXI interrupt
operation request
generated
User
processing
Figure 13-12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
Bit 0 Bit 7
1 frame
RDRF flag
cleared
to 0
RDR data read
Bit 0 Bit 1
1 frame
RXI interrupt request generated
RDR data has
not been read
(RDRF = 1)
Rev. 1.0, 03/01, page 179 of 280
Bit 6 Bit 7
ERI interrupt request
generated by
overrun error
Overrun error
processing