Hitachi H8/3672 Series Hardware Manual page 137

Table 10-2 Clock signals to input to TCNTV and the counting conditions
TCRV0
Bit 2 Bit 1
CKS2 CKS1
0 0
1
1 0
1
TCRV1
Bit 0 Bit 0
CKS0 ICKS0
−
0
1 0
1
0 0
1
1 0
1
−
0
−
1
−
0
−
1
Description
Clock input disabled
Internal clock: counts on φ/4, falling edge
Internal clock: counts on φ/8, falling edge
Internal clock: counts on φ/16, falling edge
Internal clock: counts on φ/32, falling edge
Internal clock: counts on φ/64, falling edge
Internal clock: counts on φ/128, falling edge
Clock input disabled
External clock: counts on rising edge
External clock: counts on falling edge
External clock: counts on rising and falling edge
Rev. 1.0, 03/01, page 113 of 280