Hitachi H8/3672 Series Hardware Manual page 163

TCNT value
GRA
GRB
GRC
GRD
H'0000
FTIOB
FTIOC
FTIOD
Figure 11-11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0000
H'0200
GRD
GRB
FTIOB
Figure 11-11 Buffer Operation Example (Output Compare)
Figures 11-12 and 11-13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
Counter cleared by compare match A
Figure 11-10 PWM Mode Example (2)
H'0200
H'0450
H'0200
H'0450
H'0520
H'0450
Rev. 1.0, 03/01, page 139 of 280
Time
H'0520
Time
H'0520