Hitachi H8/3672 Series Hardware Manual page 254

Mnemonic
DEC.L #1, ERd
DEC
DEC.L #2, ERd
DAS DAS.Rd
MULXU. B Rs, Rd
MULXU
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS
MULXS. W Rs, ERd
DIVXU DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
Rev. 1.0, 03/01, page 230 of 280
Addressing Mode and
Instruction Length (bytes)
L 2
L 2
B 2
B 2
W 2
B 4
W 4
B 2
W 2
B 4
W 4
B 2
B 2
W 4
W 2
L 6
L 2
Operation
I
ERd32–1 → ERd32
—
ERd32–2 → ERd32
—
Rd8 decimal adjust —
→ Rd8
Rd8 × Rs8 → Rd16
—
(unsigned multiplication)
Rd16 × Rs16 → ERd32
—
(unsigned multiplication)
Rd8 × Rs8 → Rd16
—
(signed multiplication)
Rd16 × Rs16 → ERd32
—
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
—
(RdH: remainder,
RdL: quotient)
(unsigned division)
ERd32 ÷ Rs16 → ERd32
—
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
—
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
—
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8 —
Rd8–Rs8 —
Rd16–#xx:16 —
Rd16–Rs16 —
ERd32–#xx:32 —
ERd32–ERs32 —
No. of
*1
States
Condition Code
H N Z V C
— — 2
— — 2
* * — 2
— — — — — 14
— — — — — 22
— — —
16
— — — 24
— (6) (7) — — 14
— (6) (7) — — 22
— (8) (7) — — 16
— (8) (7) — — 24
2
2
(1) 4
(1) 2
(2) 4
(2) 2