16.3
Operation Timing
OSC1
V
CC
OSC1
,
to
FTCI
FTIOA to FTIOD
TMCIV, TMRIV
TRGV
t
OSC
V
IH
V
IL
t
CPH
t
CPr
Figure 16-1 System Clock Input Timing
× 0.7
V
CC
t
REL
V
Figure 16-2 RES Low Width Timing
V
IH
V
IL
Figure 16-3 Input Timing
t
CPL
t
CPf
V
IL
t
t
IL
IH
IL
t
REL
Rev. 1.0, 03/01, page 221 of 280