Hitachi H8/3672 Series Hardware Manual page 61

Prior to executing BSET
P57
Input/output Input
Pin state Low
level
PCR5 0
PDR5 1
BSET instruction executed
BSET #0,
After executing BSET
P57
Input/output Input
Pin state Low
level
PCR5 0
PDR5 0
Description on operation
When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
P56 P55
Input Output
High Low
level level
0 1
0 0
The BSET instruction is executed for port 5.
@PDR5
P56 P55
Input Output
High Low
level level
0 1
1 0
P54 P53 P52
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
P54 P53 P52
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
Rev. 1.0, 03/01, page
P51 P50
Output Output
Low Low
level level
1 1
0 0
P51 P50
Output Output
Low High
level level
1 1
0 1
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