Hitachi H8/3672 Series Hardware Manual page 10

9.5.2 Port Data Register 8(PDR8)..................................................................................... 105
9.5.3 Pin Functions ........................................................................................................... 105
9.6 Port B ................................................................................................................................ 107
9.6.1 Port Data Register B(PDRB) ................................................................................... 108
Section 10 Timer V............................................................................................109
10.1 Features............................................................................................................................. 109
10.2 Input/Output Pins .............................................................................................................. 110
10.3 Register Descriptions ........................................................................................................ 111
10.3.1 Timer Counter V (TCNTV) ................................................................................. 111
10.3.2 Time Constant Registers A and B (TCORA, TCORB)........................................ 111
10.3.3 Timer Control Register V0(TCRV0) ................................................................... 112
10.3.4 Timer Control/Status Register V(TCSRV) .......................................................... 114
10.3.5 Timer Control Register V1(TCRV1) ................................................................... 115
10.4 Operation .......................................................................................................................... 115
10.4.1 Timer V operation................................................................................................ 115
10.5 Timer V application examples .......................................................................................... 119
10.5.1 Pulse Output with Arbitrary Duty Cycle.............................................................. 119
10.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input ............. 120
10.6 Usage Notes ...................................................................................................................... 121
Section 11 Timer W...........................................................................................123
11.1 Features............................................................................................................................. 123
11.2 Input/Output Pins .............................................................................................................. 125
11.3 Register Descriptions ........................................................................................................ 126
11.3.1 Timer Mode Register W(TMRW) ....................................................................... 126
11.3.2 Timer Control Register W(TCRW) ..................................................................... 128
11.3.3 Timer Interrupt Enable Register W(TIERW)....................................................... 129
11.3.4 Timer Status Register W(TSRW) ........................................................................ 129
11.3.5 Timer I/O Control Register 0(TIOR0) ................................................................. 131
11.3.6 Timer I/O Control Register 1(TIOR1) ................................................................. 132
11.3.7 Timer Counter (TCNT)........................................................................................ 133
11.3.8 General Registers A to D (GRA to GRD)............................................................ 133
11.4 Operation .......................................................................................................................... 134
11.4.1 Normal Operation ................................................................................................ 134
11.4.2 PWM Operation ................................................................................................... 138
11.5 Operation Timing.............................................................................................................. 142
11.5.1 TCNT Count Timing ........................................................................................... 142
11.5.2 Output Compare Timing ...................................................................................... 142
11.5.3 Input Capture Timing........................................................................................... 143
11.5.4 Timing of Counter Clearing by Compare Match ................................................. 144
11.5.5 Buffer Operation Timing ..................................................................................... 144
11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ................................ 145
Rev. 2.0, 03/01, page
x
of xxiv