Ibert Design Files; Example_Ibert_V6_Q1Xx_Top.bit - Xilinx IBERT ML628 Getting Started Manual

The directory structures for the GTH and GTX designs are identical. For example:
Has the same structure as:
The par directory contains the project, input and pre-compiled .ngc files required to
build the demonstration. The .bit configuration file is also in the par directory.

IBERT Design Files

The IBERT design files are described in this section.

example_ibert_v6_q1xx_top.bit

The example_ibert_v6_q1xx_top.bit file is the FPGA bitstream (configuration) file
for the IBERT demonstration. This file can be used to program the FPGA directly using
ChipScope or iMPACT and a JTAG download cable.
example_implement_ibert_v6_q1xx.prj
The example_implement_ibert_v6_q1xx.prj project file is used with the Xilinx
Synthesis Technology (xst) synthesis application to provide a list of files associated with
the design. The .prj file contains the language, library name (e.g., "work") and the design
files. This .prj file is referenced in the .xst file.
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
ML628_gth_q117/
par/
example_ibert_v6_q117_top.bit
example_implement_ibert_v6_q117.prj
example_implement_ibert_v6_q117.xst
i2c_sclk2_control.ngc
ibert_v6_q117.ngc
icon_v6_1.ngc
implement.bat
vio_v6_si84_so78.ngc
src/
chipscope.v
example_ibert_v6_q117.v
i2c_sclk2_control_bb.v
ibert_v6_q117_top.ucf
vio_sclk2_control.v
ML628_gtx_q100/
par/
example_ibert_v6_q100_top.bit
example_implement_ibert_v6_q100.prj
example_implement_ibert_v6_q100.xst
i2c_sclk2_control.ngc
ibert_v6_q100.ngc
icon_v6_1.ngc
implement.bat
vio_v6_si84_so78.ngc
src/
chipscope.v
example_ibert_v6_q100.v
i2c_sclk2_control_bb.v
ibert_v6_q100_top.ucf
vio_sclk2_control.v
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IBERT Demonstration Designs
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