Dvi Codec - Xilinx ML605 User Manual

14. DVI Codec

The ML605 features a DVI connector (P3) to support an external video monitor. The DVI
circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit
color. The video interface chip drives both the digital and analog signals to the DVI
connector. A DVI monitor can be connected to the board directly. A VGA monitor can also
be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel
CH7301C is controlled by way of the video IIC bus.
The DVI connector
monitor's configuration parameters. These parameters can be read by the FPGA using the
DVI IIC bus (see
Table 1-17: DVI Controller Connections
U1 FPGA Pin Schematic Net Name
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010
(Table 1-17) supports the IIC protocol to allow the board to read the
"15. IIC Bus," page
AJ19 DVI_D0
AH19 DVI_D1
AM17 DVI_D2
AM16 DVI_D3
AD17 DVI_D4
AE17 DVI_D5
AK18 DVI_D6
AK17 DVI_D7
AE18 DVI_D8
AF18 DVI_D9
AL16 DVI_D10
AK16 DVI_D11
AD16 DVI_DE
AN17 DVI_H
AP17 DVI_RESET_B_LS
AD15 DVI_V
AC17 DVI_XCLK_N
AC18 DVI_XCLK_P
No Connect DVI_GPIO0
No Connect DVI_GPIO1
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42).
U38 Chrontel CH7301C
Pin Number
63
62
61
60
59
58
55
54
53
52
51
50
2
4
13
5
56
57
8
7
Detailed Description
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DE
H
RESET_B
V
XCLK_N
XCLK_P
GPIO0
GPIO1
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