Stereo Ac97 Audio Codec; Rs-232 Serial Port; Character X 2-Line Lcd - Xilinx M401 User Manual

Detailed Description

11. Stereo AC97 Audio Codec

The ML40x board has an AC97 audio codec (U14) to permit audio processing. The
National Semiconductor LM4550 Audio Codec supports stereo 16-bit audio with up to
48-kHz sampling. The sampling rate for record and playback can be different.
Note:
is designed to be asserted at power-on or upon system reset.
Separate audio jacks are provided for Microphone, Line In, Line Out, and Headphone. All
jacks are stereo except for Microphone. The Headphone jack is driven by the audio codec's
internal 50-mW amplifier.
Table 12: ML40x Audio Jacks

12. RS-232 Serial Port

The ML40x board contains one male DB-9 RS-232 serial port allowing the FPGA to
communicate serial data with another device. The serial port is wired as a host (DCE)
device. Therefore, a null modem cable is normally required to connect the board to the
serial port on a PC. The serial port is designed to operate up to 115200 Bd. An interface chip
is used to shift the voltage level between FPGA and RS-232 signals.
Note:
RS-232 signals, including hardware flow control signals, are not used. Flow control should be
disabled when communicating with a PC.
A secondary serial interface is available by using header J27 to support debug of the USB
controller chip. Header J27 brings out RS-232 voltage level signals for ground, TX data, and
RX data.

13. 16-Character x 2-Line LCD

The ML40x board has a 16-character x 2-line LCD (Lumex LCM-S01602DTR/M) on the
board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The
data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level
translator chip is used to shift the voltage level between the FPGA and the LCD.
www.BDTIC.com/XILINX
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The reset for the AC97 codec is shared with the reset signal for the flash memory chips and
Table 12
Reference
Function
Designator
J11 Microphone - In
J12 Analog Line - In
J13 Analog Line - Out
J14 Headphone - Out
The FPGA is only connected to the TX and RX data pins on the serial port. Therefore, other
Caution!
Care should be taken not to scratch or damage the surface of the LCD window. The
protective layer of tape on the top of the screen should be left on for added protection of the
screen's surface.
www.xilinx.com
summarizes the audio jacks.
Stereo/Mono
Mono
Stereo
Stereo
Stereo
ML401/ML402/ML403 Evaluation Platform
R
UG080 (v2.5) May 24, 2006