Registers Controlling Watchdog Timer - NEC 78K0S/KA1+ User Manual

9.3

Registers Controlling Watchdog Timer

The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Reset signal generation sets this register to 67H.
Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF48H After reset: 67H
7
Symbol
0
WDTM
Note 1
WDCS4 WDCS3
0
0
1
Note 2
WDCS2 WDCS1
0
0
0
0
1
1
1
1
Notes 1. If "low-speed internal oscillator cannot be stopped" is specified by the option byte, this cannot
be set. The low-speed internal oscillation clock will be selected no matter what value is
written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
CHAPTER 9 WATCHDOG TIMER
R/W
6 5 4
1 1 WDCS4
Note 1
0 Low-speed internal oscillation clock (f
1 System Clock (f )
X
× Watchdog timer operation stopped
Note 2 Note 2
WDCS0
During low-speed internal
oscillation clock operation
11
0 0 2 /f (4.27 ms)
RL
12
0 1 2 /f (8.53 ms)
RL
13
1 0 2 /f (17.07 ms)
RL
14
1 1 2 /f (34.13 ms)
RL
15
0 0 2 /f (68.27 ms)
RL
16
0 1 2 /f (136.53 ms)
RL
17
1 0 2 /f (273.07 ms)
RL
18
1 1 2 /f (546.13 ms)
RL
User's Manual U16898EJ3V0UD
3 2
WDCS3 WDCS2 WDCS1
Operation clock selection
)
RL
Overflow time setting
During system clock operation
13
2 /f (819.2
X
14
2 /f (1.64 ms)
X
15
2 /f (3.28 ms)
X
16
2 /f (6.55 ms)
X
17
2 /f (13.11 ms)
X
18
2 /f (26.21 ms)
X
19
2 /f (52.43 ms)
X
20
2 /f (104.86 ms)
X
1 0
WDCS0
µ
s)
147