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Intel MCS-5 User Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Architectural Overview
Table of Contents
Program Memory
Data Memory
The Mcsb 51 Instruction Set
Program Status Word
Addressing Modes
Arithmetic Instructions
Logical Instructions
Data Transfers
Boolean Instructions
Relative Offset
Jump Instructions
Cpu Timing
Machine Cycles
Interrupt Priorities
Interrupt Enables
Additional References
Memory Organization
Program Memory
Mcs" 51 Programmer'sguide and
Data Memory
Indirect Address Area
Direct and Indirect Address Area
Special Function Registers
WHAT DO the Sfrs CONTAIN JUST after POWER-ON or a RESET
Sfr Memory Map
Psw: Program Status Word Bit Addressable
Pcon: Power Control Register Not Bit Addressable
Interrupts
Ie: Interrupt Enable Register Bit Addressable
Assigning Higher Priority to One or more Interrupts
Priority Within Level
Ip: Interrupt Priority Register Bit Addressable
Bit Addressable
Addressable
Timer Setup
Bit Addressable
Timer/Counter 2 Set-Up
Serial Port Setup
Generating Baud Rates
Using Timer/Counter 1 to Generate Baud Rates
Using Timer/Counter 2 to Generate Baud Rates
Mcs@-51 Instruction Set
Instruction Opcodes
Operation
Special Function Registers
Hardware Description
Port Structures and Operation
Writing to a Port
Port Loading and Interfacing
Read-Modify-Write F
Accessing External Memory
Timericounters
Timer and Timer
Serial Interface
Multiprocessor Communications
Serial Port Control Register
Baud Rates
Serial Port Mode
Timer2
Interrupts
Priority Level Structure
How Interrupts Are Handled
External Interrupts
Response Time
Single-Step Operation
Reset
Power-On Reset
Power-Saving Modes of Operation
CHMOS Power Reduction Modes
Idle Mode
Eprom Versions
Exposure to Light
Program Memory Locks
The On-Chip Oscillators
Internal Timing
Additional References
Introduction
Pin Description
Data Memory
Special Function Registers
Timer 2
Capture Mode
AUTO-RELOAD (up or down Counter)
Baud Rate Generator
Programmable Clock out
Power down Mode
Power off Flag
Once Mode
Additional References
Memory Organization
Special Function Registers
Port Structures and Operation
Read-Modify-Write Feature
Timer 0 and Timer 1
AUTO-RELOAD (up or
Timer
Auto-Reload Mode
Programmable Counter
Array
Captureicompare Modules
16-Bit Capture Mode
16-Bit Software Timer Mode
High Speed Output Mode
Watchdog Timer Mode
Pulse Width Modulator Mode
Baud Rate Generator
Interrupts
Interrupt Priority Structure
Power-On Reset
Power-Saving Modes of Operation
Power down Mode
Power off Flag
Program Memory Lock
On-Chip Oscillator
Introduction to the 8Xc51Gb
Memory Organization
Program Memory
Special Function
Port Loading and Interfacing
Read-Modify-Write Instructions
Accessing External Memory
Timer 0 and Timer
Mode 0
Mode 1
Mode 2
Mode 3
Timer 2
Timer 2 Capture Mode
Timer 2 Auto-Reload Mode
Programmable Clock out
A/D Special Function Registers
AID Comparison Mode
A/D Input Modes
Using the A/D with Fewer than
A/D in Power down
Programmable Counter
Array
Reading the PCA Timer
Com Parelcapture Modules
PCA Capture Mode
Software Timer Mode
High Speed Output Mode
Watchdog Timer Mode
Serial Port
Framing Error Detection
Multiprocessor Communications
Baud Rates
Automatic Address Recognition
Baud Rates
Timer 1 to Generate Baud
Timer 2 to Generate Baud
Timer
Serial Expansion Port
Hardware Watchdog Timer
Using the WDT
WDT During Power down and
Oscillator Fail Detect
Interrupts
External Interrupts
OFD During Power down
Timer Interrupts
Serial Port Interrupt
Serial Port Interrupt
Interrupt Processing
Interrupt Response Time
Reset
Power-Saving Modes
Operation
Once Mode
Memory
Epromiotp Programming
Program Lock Bits
Cpu Timing
Comparison of 80C152 and 80C51 Bh Features
Memory Space
Special Function
Data Memory
Program Memory
Interrupt Structure
Reset
Pin Description
Power down and Idle
Local Serial Channel
Global Serial Channel
Introduction
CSMAICD Operation
Collision Detection
SDLC Operation
Data Encoding
User Defined Protocols
Using the GSC
Test Modes
External Clocking
Register Descriptions
Serial Backplane Vs Network
Dma Operation
DMA with the 80C152
Burst Mode
Timing Diagrams
Hold/Hold Acknowledge
DMA Arbitration
Summary of DMA Control Bits
Interrupt Structure
GSC Transmitter Error
Conditions
Gsc
Conditions
Glossary
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MCS" 51 MICROCONTROLLER
FAMILY USER'S MANUAL
ORDER NO.: 272383-002
FEBRUARY 1994
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