Texas Instruments TUSB3210 Data Manual
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Texas Instruments TUSB3210 Data Manual

Texas Instruments TUSB3210 Data Manual

Universal serial bus general-purpose device controller
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TUSB3210
Universal Serial Bus General Purpose Device
Controller
NOTE
Designing with this device may require extensive support. Before incorporating this device into
a design, customers should contact TI or an Authorized TI Distributor.
February 2001
Data Manual
MSDS Bus Solutions
SLLS466

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Summary of Contents for Texas Instruments TUSB3210

  • Page 1 TUSB3210 Universal Serial Bus General Purpose Device Controller Data Manual NOTE Designing with this device may require extensive support. Before incorporating this device into a design, customers should contact TI or an Authorized TI Distributor. February 2001 MSDS Bus Solutions...
  • Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.

  • Page 3: Table Of Contents

    ........2–2 2.2.1 TUSB3210 Boot Operation ......2–2 2.2.2...
  • Page 4 2.6.2 USBSTA: USB Status Register ..... . . 2–14 2.6.3 USBMSK: USB Interrupt Mask Register ....2–15 2.6.4 USBCTL: USB Control Register...
  • Page 5 1–2 2–1 MCU Memory Map (TUSB3210) ........

  • Page 7: Introduction

    1 Introduction The TUSB3210 has 8k × 8 RAM space for application development. A ROM based version of the TUSB3210 has 8k × 8 ROM space for predeveloped customer specific production applications. In addition, the programmability of the TUSB3210 makes it flexible enough to use for various other general USB I/O applications. Unique vendor identification and product identification (VID/PID) may be selected without the use of an external EEPROM.

  • Page 8: Functional Block Diagram

    I 2 C I 2 C Bus Suspend/ Controller Resume USB Buffer Manager Control Logic [1] The TUSB3210 has 8K x 8 RAM for development. 8k x 8 ROM version available. Contact TI Marketing Figure 1–1. TUSB3210 Block Diagram 1–2...

  • Page 9: Terminal Assignments

    1.3 Terminal Assignments PM PACKAGE (TOP VIEW) 47 46 45 44 43 40 39 38 37 36 35 34 33 P0.6 P1.1 P0.7 P1.0 P3.7 P2.7 P3.6 P2.6 P3.5 P2.5 P3.4 P2.4 P3.3 P2.3 P3.2 P2.2 P3.1/S1 P3.0/S0 P2.1 P2.0 SELF/BUS TEST2 1 2 3...

  • Page 10: Terminal Functions

    1.5 Terminal Functions TERMINAL DESCRIPTION DESCRIPTION NAME Differential data minus USB Differential data plus USB 5,24,42,5 Power supply ground 2, 3, 6, No connection 7, 63, 64 General-purpose I/O port 0 bit 0, Schmitt-trigger input 100 µA active pullup, open drain output P0.0 General-purpose I/O port 0 bit 1, Schmitt-trigger input 100 µA active pullup, open drain output P0.1...
  • Page 11 1.5 Terminal Functions (Continued) TERMINAL DESCRIPTION DESCRIPTION NAME Serial clock I 2 C; open drain output Serial data I 2 C; open drain output SELF/BUS USB power MODE select: self-powered (HIGH), bus-powered (LOW) SUSP Suspend status signal: suspended (HIGH); unsuspended (LOW) Test input0, Schmitt-trigger input 100 µA active pullup TEST0 Test input1, Schmitt-trigger input 100 µA active pullup...
  • Page 12 1–6...

  • Page 13: Functional Description

    Code RAM Code RAM Read/Write Read Only 1FFF 8000 6k Boot ROM 6k Boot ROM 6k Boot ROM 6k Boot ROM 97FF FD80 512 Bytes 512 Bytes 512 Bytes 512 Bytes FF80 FFFF Figure 2–1. MCU Memory Map (TUSB3210) 2–1...

  • Page 14: Miscellaneous Registers

    TUSB3210 Boot Operation Since the code-space is in RAM (with the exception of the boot ROM), the TUSB3210 firmware must be loaded from an external source. Two options for booting are available: an external serial EEPROM source connected to the I bus, or the host may be used via the USB.

  • Page 15: Mcnfg: Mcu Configuration Register

    2.2.2 MCNFG: MCU Configuration Register This register is used to control the MCU clock rate. 12/48 XINT NAME RESET FUNCTION This bit enables/disables boot ROM. In the ROM version of the controller, this bit has no effect. SDW = 0 When clear, MCU executes from the 6k boot ROM space.

  • Page 16: Wdcsr: Watchdog Timer, Control, And Status Register

    2.2.5 WDCSR: Watchdog Timer, Control, and Status Register A watchdog timer (WDT) with 1ms clock is provided. If this register is not accessed for a period of 32ms, the WDT counter will reset the MCU. (See Figure 2–3, Reset Diagram). When the IDL bit in PCON is set, the WDT will be suspended until an interrupt is detected.
  • Page 17 Table 2–1. XDATA Space DESCRIPTION ADDRESS RANGE FFFF Internal MMR Internal MMR l MMR ↑ ↑ (Memory mapped registers) (Memory mapped registers) FF80 FF7F ↑ (Endpoint descriptor blocks) (Endpoint descriptor blocks) FF08 FF07 ↑ Setup packet buffer Setu acket buffer FF00 FEFF 512 b t...
  • Page 18 Table 2–2. Memory Mapped Registers Summary (XDATA Range = FF80 → FFF) (Continued) ADDRESS REGISTER DESCRIPTION FF91 RESERVED FF90 MCNFG MCNFG: MCU configuration register ↑ RESERVED FF84 INTCFG INTCFG: Interrupt delay configuration register FF83 OEPBCNT_0 OEPBCNT_0: Output endpoint-0 byte count register FF82 OEPCNFG_0 OEPCNFG_0: Output endpoint-0 configuration register...

  • Page 19: Endpoint Descriptor Block (Edb-1 To Edb-3)

    Table 2–3. EDB and Buffer Allocations in XDATA (Continued) ADDRESS DESCRIPTION FEF7 ↑ (8–bytes) (8 bytes) Output endpoint_0 buffer Out ut end oint_0 buffer FEF0 FEEF TOPBUFF Top of buffer space ↑  Buffers space  FD80 STABUFF Start of buffer space 2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB).

  • Page 20: Oepbbax_N: Output Endpoint X-Buffer Base-Address

    2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address (n=1 to 3) A 10 NAME RESET FUNCTION 7–0 A[10:3] A[10:3] of X–buffer base address (padded with 3-LSB of zeros for a total of 11-bits). This value is set by the MCU. UBM or DMA uses this value as the start-address of a given transaction. Furthermore, UBM or DMA does not change this value at the end of a transaction.

  • Page 21: Oepsizxy_N: Output Endpoint X/Y Byte Count

    2.4.6 OEPSIZXY_n: Output Endpoint X/Y Byte Count (n=1 to 3) NAME RESET FUNCTION 6–0 S[6:0] X AND Y-Buffer size: 0000.0000b > Count = 0 0000.0001b > Count = 1 byte 0011.1111b > Count = 63 bytes 0100.0000b > Count = 64 bytes Any value ≥...

  • Page 22: Iepbctx_N: Input Endpoint X-Byte Base-Address

    2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base-Address (n=1 to 3) NAME RESET FUNCTION 6–0 C[6:0] X-Buffer Byte count: X000.0000b > Count = 0 X000.0001b > Count = 1 byte X011.1111b > Count = 63 bytes X100.0000b > Count = 64 bytes Any value ≥...

  • Page 23: Iepsizxy_N: Input Endpoint X/Y-Buffer Size

    2.4.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size (n=1 to 3) NAME RESET FUNCTION 6–0 S[6:0] X AND Y-Buffer size: 0000.0000b > Count = 0 0000.0001b > Count = 1 byte 0011.1111b > Count = 63 bytes 0100.0000b > Count = 64 bytes Any value ≥...

  • Page 24: Iepbcnt_0: Input Endpoint-0 Byte Count Register

    2.5.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register NAME RESET FUNCTION 3–0 C[3:0] 0000 Byte count: 0000b > Count = 0 0111b > Count =7 1000b > Count = 8 1001b to 1111b are reserved. (If used, defaults to 8) 6–4 Reserved NAK= 0 Buffer contains a valid packet for host-in transaction NAK= 1 Buffer is empty (host-in request is NAK)

  • Page 25: Usb Registers

    2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register NAME RESET FUNCTION 3–0 C[3:0] 0000 Byte count: 0000b > Count = 0 0111b > Count =7 1000b > Count = 8 1001b to 1111b are reserved. (If used, defaults to 8) 6–4 Reserved = 0 NAK= 0 No valid data in buffer.

  • Page 26: Usbsta: Usb Status Register

    2.6.2 USBSTA: USB Status Register All bits in this register are set by the hardware and will be cleared by MCU when writing a 1 to the proper bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C notation indicates read and clear only by MCU).

  • Page 27: Usbmsk: Usb Interrupt Mask Register

    2.6.3 USBMSK: USB Interrupt Mask Register RSTR SUSR RESR PWOFF PWON SETUP STPOW NAME RESET FUNCTION STPOW SETUP overwrite interrupt enable bit STPOW = 0 STPOW interrupt disabled STPOW = 1 STPOW interrupt enabled Reserved = 0 SETUP SETUP interrupt enable bit SETUP = 0 SETUP interrupt disabled SETUP = 1 SETUP interrupt enabled PWON...

  • Page 28: Usbctl: Usb Control Register

    This register is used to read the value on four external pins. The firmware can use this value to select one of the vendor identification/product identifications (VID/PID) stored in memory. The TUSB3210/D supports up to 16 unique VID/PIDs with application code to support different products. This provides a unique opportunity for original equipment manufacturers (OEM) to have one device ROM programmed to support up to 16 different product lines by using S0–S3 to select VID/PID and behavioral application code for the selected product.

  • Page 29: Function Reset And Power-Up Reset Interconnect

    Table 2–6. External Pins Mapping to S[3:0] in VIDSTA Register VIDSTA REGISTER COMMENTS COMMENTS NAME S[3:0] P3.0 Dual function P3.0 I/O or S0 input P3.1 Dual function P3.1 I/O or S1 input S2-pin is input S3-pin is input 2.7 Function Reset and Power-Up Reset Interconnect Figure 2–3 represents the logical connection of USB-function-reset (USBR) and power-up-reset (RST-pin).

  • Page 30: Pullup Resistor Connect/Disconnect

    2.8 Pullup Resistor Connect/Disconnect After reading firmware into RAM the TUSB3210 can re-enumerate using the new firmware (no need to physically disconnect and re-connect the cable). Figure 2–4 shows an equivalent circuit implementation for Connect and Disconnect from a USB up-stream port (also see Firgure 4–4b). When CONT bit in USBCTL register is 1, the CMOS...

  • Page 31: 8052 Standard Interrupt Enable Register

    2.9.1 8052 Standard Interrupt Enable Register NAME RESET FUNCTION Enable or disable external interrupt-0 EX0 = 0 external interrupt-0 is disabled EX0 = 1 external interrupt-0 is enabled Enable or disable timer-0 interrupt ET0 = 0 timer-0 interrupt is disabled ET0 = 1 timer-0 interrupt is enabled Enable or disable external interrupt-1 EX1 = 0 external interrupt-1 is disabled...

  • Page 32: Vecint: Vector Interrupt Register

    2.9.3 VECINT: Vector Interrupt Register This register contains a vector value identifying the internal interrupt source that trapped to location . Writing 0003H any value to this register removes the vector and update the next vector value (if another interrupt is pending). Note that the vector value is offset.

  • Page 33: Logical Interrupt Connection Diagram (Int0)

    2.9.4 Logical Interrupt Connection Diagram (INT0) Figure 2–5 represents the logical connection of the interrupt sources and its relation with XINTO#. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hard wired.

  • Page 34: I2C Registers

    2.10 I2C Registers 2.10.1 I2CSTA: I2C Status and Control Register This register is used to control the stop condition for read and write operation. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits. NAME RESET FUNCTION Stop write condition.

  • Page 35: I2Cadr: I2C Address Register

    2.10.2 I2CADR: I2C Address Register This register holds the device address and the read/write command bit. NAME RESET FUNCTION Read/write command bit. R/W = 0 Write operation R/W = 1 Read operation 7–1 A[6:0] 0000000 Seven address bits for device addressing. 2.10.3 I2CDAI: I2C Data-Input Register This register holds the received data from an external device.

  • Page 36: Current Address Read Operation

    • The content of I2CADR register is transmitted to the EEPROM (preceded by start condition on SDA) • The content of I2CDAO register is transmitted to the EEPROM (EEPROM address) • TXE bit in I2CSTA is set, and interrupts the MCU, indicating that I2CDAO register has been transmitted •...

  • Page 37: Write Operation (Serial Eeprom)

    • MCU reads I2CDAI register, clearing RXF bit (I2CSTA[RXF] = 0) • This operation repeats 31 times 3. Last-Byte read (byte No. 32) • MCU sets I2CSTA[SRD] = 1. This forces the I2C controller to generate a stop condition after I2CDAI register is received •...

  • Page 38: Page Write Operation

    2.11.5 Page Write Operation Page write operation is initiated the same way as byte write, with the exception that stop condition is not generated after the first EEPROM [DATA] is transmitted. The following describes the sequence of writing 32-bytes in page mode: Device Address + EEPROM [High-byte] •...

  • Page 39: Electrical Specifications

    3 Electrical Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature † (unless otherwise noted) Supply voltage, V ..............–0.5 V to 4 V Input voltage, V .
  • Page 40 3–2...

  • Page 41: Application

    P3[7:4] can sink up to 12 mA (open-drain output). Figure 4–2 illustrates the partial connection bus power mode. Figure 4–3 shows the USB upstream connection, and Figure 4–4 illustrates the downstream connection (only one port shown). V CC TUSB3210 P3.2 P3.3 P3.4 P3.5...

  • Page 42: Reset Timing

    Bus PWR 3.3 V (5 V) 1.5 kΩ 1.5 kΩ D– D– Figure 4–3. Upstream Connection (a) Non-Switching Power Mode (b) Switching Power Mode To Power Switch D– 15 kΩ 15 kΩ NOTE: Ferrite beads can be used on power lines to help ESD. Figure 4–4.

  • Page 43: Mechanical Data

    5 Mechanical Data PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 7,50 TYP Gage Plane 10,20 9,80 0,25 12,20 0,05 MIN 0°– 7° 11,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A.
  • Page 44 5–2...

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