11.3.9
Memory Submenu
Feature
Memory Clock
Bank Interleaving
Channel Interleaving
Memory Clear
ECC Support
Dimm0
Dimm1
11.3.10
Chipset Submenu
Feature
Chipset Power Saving Features
Spread Spectrum Clocking
Spread Spectrum Level
HPET
IOMMU
Copyright © 2016 congatec AG
Options
Description
Auto
Set upper memory frequency limit. Auto is a maximum values supported by SoC and SPD
1333 Mhz
data of inserted memory modules.
1600 Mhz
1866 Mhz
2133 Mhz
Enabled
Enable or disable DRAM bank interleaving.
Disabled
Enabled
Enable or disable DRAM channel interleaving.
Disabled
Enabled
Enable or disable memory clear on reset.
Disabled
Enabled
Enable or disable ECC support. ECC can be enabled only if all inserted memory modules
Disabled
are supporting it.
No option
Size, current speed and SPD max speed of DIMM 0 module
No option
Size, current speed and SPD max speed of DIMM 1 module
Options
Enabled
Disabled
Enabled
Disabled
-0.362%
-0.375%
-0.400%
-0.425%
-0.450%
-0.475%
Enabled
Disabled
Enabled
Disabled
Description
Enable or disable chipset power saving.
Enable or disable spread spectrum of chipset's PLL. Required to be enabled for full USB 3.0
compliance. System generates additional soft reset after each hard reset or power-on to enable SSC.
Select spread spectrum level, if previous option is enabled.
Enabled or disable High Performance Event Timer.
Enable or disable IO Memory-Mapping Unit.
TR33m10
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