Table 25 Serial/Uart Interface Signal Descriptions; Table 26 Power And Gnd Signal Descriptions - Congatec COM Express conga-TR3 User Manual

3rd generation amd embedded r-series soc
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Signal
Pin # Description
BATLOW#
A27
Battery low input. This signal may be driven low by external circuitry to signal that
the system battery is low, or may be used to signal some other external power-
management event.
THRM#
B35
Input from off-module temp sensor indicating an over-temp situation.
THERMTRIP#
A35
Active low output indicating that the CPU has entered thermal shutdown.
SMB_CK
B13
System Management Bus bidirectional clock line.
SMB_DAT#
B14
System Management Bus bidirectional data line.
SMB_ALERT#
B15
System Management Bus Alert – active low input can be used to generate an
SMI# (System Management Interrupt) or to wake the system.
LID#
A103
Lid button. Used by the ACPI operating system for a LID switch.
SLEEP
B103
Sleep button. Used by the ACPI operating system to bring the system to sleep
state or to wake it up again.
Table 25
Serial/UART Interface Signal Descriptions
Signal
Pin #
Description
SER0_TX
A98
General purpose serial port transmitter
SER1_TX
A101
General purpose serial port transmitter
SER0_RX
A99
General purpose serial port receiver
SER1_RX
A102
General purpose serial port receiver
Table 26
Power and GND Signal Descriptions
Signal
Pin #
VCC_12V
A104-A109
B104-B109
VCC_5V_SBY
B84-B87
VCC_RTC
A47
GND
A1, A11, A21, A31, A41,
A51, A57, A60, A66, A70,
A80, A90, A100, A110,
B1, B11, B21, B31, B41,
B51, B60, B70, B80, B90,
B100, B110
Copyright © 2016 congatec AG
Description
Primary power input: +12V nominal. All available VCC_12V pins on the connector(s)
shall be used.
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY
pins on the connector(s) shall be used. Only used for standby and suspend functions.
May be left unconnected if these functions are not used in the system design.
Real-time clock circuit-power input. Nominally +3.0V.
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board GND plane.
I/O
PU/PD
I 3.3VSB
PU 10K 3.3VSB
I 3.3V
PU 10k 3.3V
O 3.3V
PU 10k 3.3V
I/O 3.3VSB
PU 2.2K 3.3VSB
I/O OD
PU 2.2K 3.3VSB
3.3VSB
I 3.3VSB
PU 10K 3.3VSB
I 3.3V
PU 47K 3.3VSB
I 3.3V
PU 47K 3.3VSB
I/O
PU/PD
Comment
O 3.3V
Signal is driven to logic 1 only. External PD is required.
O 3.3V
Signal is driven to logic 1 only. External PD is required.
I 3.3V
PU 47K 3.3V
I 3.3V
PU 47K 3.3V
TR33m10
Comment
Not supported
I/O
PU/PD Comment
P
P
P
P
52/105

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