Table 32 Hdmi/Dvi Signal Descriptions - Congatec COM Express conga-TR3 User Manual

Table 32 HDMI/DVI Signal Descriptions
Signal Pin # Description
TMDS1_CLK + D36 HDMI/DVI TMDS Clock output differential pair.
TMDS1_CLK - D37 Multiplexed with DDI1_PAIR3+ and DDI1_PAIR3-.
TMDS1_DATA0+ D32 HDMI/DVI TMDS differential pair.
TMDS1_DATA0- D33 Multiplexed with DDI1_PAIR2+ and DDI1_PAIR2-.
TMDS1_DATA1+ D29 HDMI/DVI TMDS differential pair.
TMDS1_DATA1- D30 Multiplexed with DDI1_PAIR1+ and DDI1_PAIR1-..
TMDS1_DATA2+ D26 HDMI/DVI TMDS differential pair.
TMDS1_DATA2- D27 Multiplexed with DDI1_PAIR0+ and DDI1_PAIR0-.
HDMI1_HPD C24 HDMI/DVI Hot-plug detect.
Multiplexed with DDI1_HPD.
HDMI1_CTRLCLK D15 HDMI/DVI I
Multiplexed with DDI1_CTRLCLK_AUX+
HDMI1_CTRLDATA D16 HDMI/DVI I
Multiplexed with DDI1_CTRLDATA_AUX-
TMDS2_CLK + D49 HDMI/DVI TMDS Clock output differential pair..
TMDS2_CLK - D50 Multiplexed with DDI2_PAIR3+ and DDI2_PAIR3-.
TMDS2_DATA0+ D46 HDMI/DVI TMDS differential pair.
TMDS2_DATA0- D47 Multiplexed with DDI2_PAIR2+ and DDI2_PAIR2-.
TMDS2_DATA1+ D42 HDMI/DVI TMDS differential pair.
TMDS2_DATA1- D43 Multiplexed with DDI2_PAIR1+ and DDI2_PAIR1-.
TMDS2_DATA2+ D39 HDMI/DVI TMDS differential pair.
TMDS2_DATA2- D40 Multiplexed with DDI2_PAIR0+ and DDI2_PAIR0-..
HDMI2_HPD D44 HDMI/DVI Hot-plug detect.
Multiplexed with DDI2_HPD
HDMI2_CTRLCLK C32 HDMI/DVI I
Multiplexed with DDI2_CTRLCLK_AUX+
HDM12_CTRLDATA C33 HDMI/DVI I
Multiplexed with DDI2_CTRLDATA_AUX-
TMDS3_CLK + C49 HDMI/DVI TMDS Clock output differential pair..
TMDS3_CLK - C50 Multiplexed with DDI3_PAIR3+ and DDI3_PAIR3-.
TMDS3_DATA0+ C46 HDMI/DVI TMDS differential pair.
TMDS3_DATA0- C47 Multiplexed with DDI3_PAIR2+ and DDI3_PAIR2-.
TMDS3_DATA1+ C42 HDMI/DVI TMDS differential pair.
TMDS3_DATA1- C43 Multiplexed with DDI3_PAIR1+ and DDI3_PAIR1-..
TMDS3_DATA2+ C39 HDMI/DVI TMDS differential pair.
TMDS3_DATA2- C40 Multiplexed with DDI3_PAIR0+ and DDI3_PAIR0-.
HDMI3_HPD C44 HDMI/DVI Hot-plug detect.
Multiplexed with DDI3_HPD.
HDMI3_CTRLCLK C36 HDMI/DVI I
Multiplexed with DDI3_CTRLCLK_AUX+
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C Control Clock
2
2 C Control Data
C Control Clock
2
2 C Control Data
2 C Control Clock
I/O PU/PD Comment
O PCIE
O PCIE
O PCIE
O PCIE
I PCIE PD 100K
OD 3.3V PD 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.
I/OD 3.3V PU 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.
3.3V
O PCIE
O PCIE
O PCIE
O PCIE
I PCIE PD 100K
OD 3.3V PD 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.
I/OD 3.3V PU 100K 2.2k to 3.3V Pull-up must be implemented on the carrier board.
3.3V
O PCIE Not supported by default.
O PCIE Not supported by default.
O PCIE Not supported by default.
O PCIE Not supported by default.
I PCIE PD 100K Not supported by default.
OD 3.3V PD 100K 2.2k to 3.3V Pull-up should be implemented on the carrier board.
TR33m10 60/105