Table 16 Pci Express Signal Descriptions (General Purpose); Table 17 Expresscard Support Pins Descriptions - Congatec COM Express conga-TR3 User Manual

Table 16 PCI Express Signal Descriptions (general purpose)
Signal Pin # Description
PCIE_RX0+ B68 PCI Express channel 0, Receive Input differential pair.
PCIE_RX0- B69
PCIE_TX0+ A68 PCI Express channel 0, Transmit Output differential pair.
PCIE_TX0- A69
PCIE_RX1+ B64 PCI Express channel 1, Receive Input differential pair.
PCIE_RX1- B65
PCIE_TX1+ A64 PCI Express channel 1, Transmit Output differential pair.
PCIE_TX1- A65
PCIE_RX2+ B61 PCI Express channel 2, Receive Input differential pair.
PCIE_RX2- B62
PCIE_TX2+ A61 PCI Express channel 2, Transmit Output differential pair.
PCIE_TX2- A62
PCIE_RX3+ B58 PCI Express channel 3, Receive Input differential pair.
PCIE_RX3- B59
PCIE_TX3+ A58 PCI Express channel 3, Transmit Output differential pair.
PCIE_TX3- A59
PCIE_RX4+ B55 PCI Express channel 4, Receive Input differential pair.
PCIE_RX4- B56
PCIE_TX4+ A55 PCI Express channel 4, Transmit Output differential pair.
PCIE_TX4- A56
PCIE_RX5+ B52 PCI Express channel 5, Receive Input differential pair.
PCIE_RX5- B53
PCIE_TX5+ A52 PCI Express channel 5, Transmit Output differential pair.
PCIE_TX5- A53
PCIE_CLK_REF+ A88 PCI Express Reference Clock output for all PCI Express
PCIE_CLK_REF- A89 and PCI Express Graphics Lanes.
Table 17 ExpressCard Support Pins Descriptions
Signal Pin # Description
EXCD0_CPPE# A49 ExpressCard capable card request.
EXCD1_CPPE# B48
EXCD0_PERST# A48 ExpressCard Reset
EXCD1_PERST# B47
Copyright © 2016 congatec AG
I/O PU/PD
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
O PCIE
I/O PU/PD Comment
I 3.3VSB PU 10k 3.3VSB
O 3.3V
TR33m10
Comment
Supports PCI Express Base Specification, Revision 3.0
Supports PCI Express Base Specification, Revision 3.0
Supports PCI Express Base Specification, Revision 3.0
Supports PCI Express Base Specification, Revision 3.0
Supports PCI Express Base Specification, Revision 3.0
Supports PCI Express Base Specification, Revision 3.0
Not connected by default.
Not connected by default.
Not connected
Not connected
Not connected
Not connected
A PCI Express Gen2/3 compliant clock buffer chip must be used
on the carrier board if more than one PCI Express device is
designed in.
47/105