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The specification has some advantages and a potential problem.
• The advantages are that a pipelined processor won't trigger until it has
executed the loop 10 times. Requiring LP_END to be seen at least once
first ensures that the processor actually entered the loop; then, 9 more
iterations of LP_START is really the 10th iteration of the loop. Also, no
trigger occurs if the loop executes less than 10 times ƒ the analyzer sees
LP_EXIT and restarts the trigger sequence.
• The potential problem is that LP_EXIT may be too near LP_END and thus
appear on the bus during a prefetch. The analyzer will constantly restart
the sequence and will never trigger. The solution to this problem depends
on the structure of your code. You may need to experiment with different
trigger sequences to find one that captures only the data you want to view.
Triggering Examples
Single-Machine Trigger Examples
101
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Table of Contents
Troubleshooting
