Hdmi Video Output - Xilinx ZCU104 User Manual

HDMI Video Output

[Figure 2-1, callouts 10 and 11]
The ZCU104 board provides an HDMI® video output using a TI SN65DP159RGZ re-timer at
U94. The output is provided on a TE Connectivity 1888811-1 right-angle dual-stacked HDMI
type-A receptacle at P7. The SN65DP159RGZ device is a dual mode DisplayPort to
transition-minimized differential signal (TMDS) re-timer supporting digital video interface
(DVI) 1.0, HDMI 1.4b, and 2.0 output signals.
The SN65DP159RGZ device supports the dual mode standard version 1.1 type 1 and type 2
through the digital down converter (DDC) link or AUX channel. The SN65DP159RGZ device
supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K/60 Hz) 8-bits
per color high-resolution video and HDTV with 16-bit color depth at 1080p
(1920 x 1080/60 Hz). The SN65DP159RGZ device can automatically configure itself as a
re-driver at data rates <1 Gb/s, or as a re-timer at more than this data rate. This feature can
be turned off with I2C programming.
The HDMI block diagram, TX interface circuit, and RX interface circuit are shown in
Figure 3-16, Figure
circuit connections are listed in
ZCU104 Board User Guide
UG1267 (v1.1) October 9, 2018
3-17, and Figure 3-18, respectively. The XCZU7EV MPSoC U1 to HDMI
Table 3-22.
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Chapter 3: Board Component Descriptions
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