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(2) Clear operation
After a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cleared.
If a TM3 clear cause occurs, TM3 is cleared to 00H by the next count clock pulse. This means that even if a
TM3 clear cause occurs, TM3 holds the value existing at that time until the next count clock pulse is applied.
Fig. 7-126 TM3 Cleared by a Coincidence with Compare Register (CR30)
Compare register
TM3 can also be cleared by software when the CE3 bit of the timer control register (TMC0) is reset to 0.
Similarly, clear operation is performed by the count clock pulse following the resetting of CE3 bit to 0. If the
CE3 bit is set to 1 before TM3 is reset to 0 by the resetting of the CE3 bit to 0 (that is, before the first count clock
pulse is applied after the CE3 bit is reset to 0), two operations are simultaneously performed: one operation
is an operation to clear TM3 to 0, and the other operation is a count operation starting with the counting of
0.
(a) Basic operation
Count clock
TM3
count clock
n-1
TM3
(CR30)
Coincidence
between TM3
and CR30
Fig. 7-127 Clear Operation When the CE3 Bit Is Reset to 0
n-1
n
TM3
CE3
Chapter 7 Timer/Counter Units
n
0
n
Cleared here
0
1
7
209
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