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9.4 BAUD RATE GENERATOR
9.4.1 Configuration of the Baud Rate Generator for UART
Fig. 9-8 shows the configuration of the baud rate generator.
Asynchronous serial
interface
Clock synchronous
serial interface
(1) 4-bit counter
The 4-bit counter counts the internal system clock (f
by the lower four bits of the baud rate generator control register (BRGC).
(2) Frequency divider
The frequency divider divides the signal input from the 4-bit counter or an external baud rate input (ASCK),
and allows the selector at the next stage to select the clock for the baud rate.
(3) Both-edge detector
The both-edge detector detects either edge of the signal input to the ASCK pin and generates a signal having
a frequency two times as high as the ASCK input clock frequency. See Chapter 11 for details of edge detection.
9.4.2 Baud Rate Generator Control Register (BRGC)
The BRGC register is an 8-bit register that holds the clock for baud rate generation controlled according to the
internal system clock (f
CLK
Only an 8-bit manipulation instruction can be used for this register, and its use is limited to write operations. Fig.
9-9 shows the format of the register.
When the RESET signal is input, the BRGC register is reset to 00H.
Caution When a BRGC register write instruction is executed, the 4-bit counter and the frequency divider are reset. If the BRGC register is
write-accessed during transmission, the baud rate being generated is disrupted, hampering normal communication. For this
reason, do not write to the BRGC register during transmission.
Fig. 9-8 Baud Rate Generator Clock Configuration
ASIM
SCK
1
2
).
Chapter 9 Asynchronous Serial Interface
Internal bus
8
BRGC
Baud rate generator
control register
4
Coincidence
4
Clear
4-bit counter
8
8-bit timer/counter 3 output
). It generates a signal having the frequency selected
CLK
RESET
Resets writing
to BRGC
f
CLK
INTP4/ASCK
9
251
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