Interrupt Mask Register (Mk0); Interrupt Service Mode Register (Ism0); Priority Specification Flag Register (Pr0); Interrupt Service Mode Register (Ism0) Format - NEC PD78212 User Manual

µ PD78214 Sub-Series

12.2.2 Interrupt Mask Register (MK0)

The MK0 register is a 16-bit register consisting of interrupt mask flags. Each interrupt mask flag enables or disables
the corresponding interrupt request.
When the RESET signal is input, the register is set to FFFFH, thus disabling all maskable interrupts.
If an interrupt mask flag is set to 1, it inhibits acceptance of the corresponding interrupt request.
If an interrupt mask flag is reset to 0, it enables the corresponding interrupt request to be accepted as a vectored
interrupt or macro service.
7
MK0L CMK11
MK0H CSIMK STMK SRMK SERMK CMK20 PMK5 PMK4 CMK21

12.2.3 Interrupt Service Mode Register (ISM0)

The ISM0 register is a 16-bit register consisting of interrupt service mode flags.
If an interrupt service mode flag is 0, the corresponding interrupt request is handled as a vectored interrupt. If it
is 1, the corresponding interrupt request is processed by a macro service. When a macro service request is
executed a specified number of times, the interrupt service mode flag is reset to 0.
When the RESET signal is input, the register is reset to 0000H, thereby specifying vectored interrupt handling.
7
ISM0L CISM11 CISM10 CISM01 CISM00 PISM3 PISM2 PISM1 PISM0
ISM0H CSIISM STISM SRISM

12.2.4 Priority Specification Flag Register (PR0)

The PR0 register is a 16-bit register consisting of interrupt priority specification flags that determine priority with
which each interrupt is accepted. They are used to control multiple-interrupt handling.
There are two interrupt groups with respect to priority; one having higher priority and one having lower priority.
When a priority specification flag is 0, the corresponding interrupt request is specified to belong to the high-priority
group; when a priority specification flag is 1, the corresponding interrupt request is specified to belong to the
lower-priority group.
When an interrupt is accepted, the corresponding priority specification flag is sent to the ISP bit of the PSW.
306
Fig. 12-4 Interrupt Mask Register (MK0) Format
6 5 4 3
CMK10 CMK01 CMK00 PMK3
Fig. 12-5 Interrupt Service Mode Register (ISM0) Format
6 5 4 3
0 CISM20 PISM5 PISM4 CISM21
2 1 0
PMK2 PMK1 PMK0 (FFFFH when RESET signal is input)
Interrupt request flag
0 Enables interrupt
1 Disables interrupt
2 1 0
(0000H when RESET signal is input)
Interrupt service mode flags
0 Vector interrupt processing
1 Macro service processing