Chapter 4 Clock Generator; Configuration And Function; Block Diagram Of Clock Generator; External Circuit For The Clock Oscillator - NEC PD78212 User Manual

4.1 CONFIGURATION AND FUNCTION

A clock generator generates and controls the internal system clock (CLK) sent to the CPU. Fig. 4-1 shows the
configuration of the clock generator.
Remarks f : Crystal/ceramic oscillation frequency
XX
f : External clock frequency
X
f : Internal system clock frequency (= 1/2·f
CLK
The clock oscillator oscillates according to a crystal or ceramic resonator connected to pins X1 and X2. In standby
(STOP) mode, the oscillation is stopped (see Chapter 14).
The external clock can also be input. To input the external clock, input the clock signal to pin X1 and the inverted
signal to pin X2. If the external clock is input, STOP mode cannot be selected.
The frequency divider divides the output from the clock oscillator (f
external clock) by two and generates the internal system clock (CLK).
(a) Crystal/ceramic oscillation
Caution When using the clock oscillator, the adverse influence of stray capacitance must be avoided. When configuring the circuit enclosed
in a dashed line, observe the following:
• Minimize the wiring length.
• Do not let other signal lines cross this circuit.
• Keep this circuit away from lines through which a varying high current flows.
• Always ground the capacitors of the oscillator at the same potential as V
through which a high current flows.
• Do not draw signals from the oscillator.

CHAPTER 4 CLOCK GENERATOR

Fig. 4-1 Block Diagram of Clock Generator
X1
f
XX
Clock
oscillator
X2
STOP mode
or 1/2·f )
XX X
Fig. 4-2 External Circuit for the Clock Oscillator
µ
PD78214
V
SS
X1
X2
Frequency
divider
or f f
X CLK
1/2
for the crystal/ceramic oscillation, f
XX
(b) External clock
µ
PD78214
X1
X2
74HC04, etc.
. Do not ground the capacitors to a ground pattern
SS
Internal system
clock (CLK)
for the
X
4
#
#
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