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Caution If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set to 1) when the RFLV bit is changed
from 0 to 1, pin REFRQ may output a glitch, having a peak level of approximately 2.6 V, for approximately 10 ns.
When setting the RFLV bit to 1, follow the steps shown in Fig. 13-22. The 200-ns delay after setting RFEN assures the access disabled
time when pseudo static RAM returns from self-refresh mode.
Fig. 13-22 Return from Self-Refresh
Self-refresh mode
Clear RFEN bit to 0
Set RFLV bit to 1
RFLV = 1
Yes
Set RFEN bit to 1
Approximately 200 ns delay
Pulse refresh mode (normal operation)
Chapter 13 Local Bus Interface Function
No
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