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µ PD78214 Sub-Series
Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A)
Caution When the external memory is expanded (or always with the µ PD78213), an illegal write access operation may occur during the type
A macro service.
This illegal write access occurs when either of the following two conditions is satisfied.
(1) When data D0H through DFH is transferred from memory to an SFR.
(2) When macro service transfers data from an SFR to a buffer (memory) at 0FED0H through 0FEDFH.
An illegal write access is processed in the same manner as the normal memory access. In addition, wait states may be inserted
according to the setting of the PW20 and PW21 bits of the memory expansion mode register (MM). Table 12-9 lists the conditions
under which an illegal write access occurs and the corresponding operations.
Table 12-9 Illegal Write Access Conditions and Corresponding Operations
Condition
This problem may be solved by either of the following two methods.
(1) It is difficult for software to solve the problem if it occurs under condition 1, because it depends on the transfer data. Therefore,
use an external address decoder circuit to keep the image in the area of 0FF00H through 0FFFFH from overlapping the memory
addresses of the external circuit.
(2) If the macro service to be used does not satisfy condition 1 (i.e., if data is not transferred from an SFR to memory), and under
condition 2, locate the buffer area so that its addresses are not 0FED0H through 0FEDFH.
The above problem also occurs with an in-circuit emulator.
324
Interrupt request specifying
the type A macro service
INTC10
INTC11
INTC20
INTC21
INTC30
INTSR
INTST
INTCSI
INTAD
INTP0
INTP1
INTP2
Address
1
Address of a destination SFR
2
Address of a source SFR
Transfer source/destination SFR
CR10 register
CR11 register
CR20 register
CR21 register
CR30 register
RXB register
TXS register
SIO register
ADCR register
CR11 register
CR22 register
TM2 register
Illegal write access
Data
Data transferred by macro service
Lower 8 bits of the address of
the destination buffer (memory)
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